A memory test apparatus has a fail memory (hereinafter, also FM) that stores therein a fail bit map obtained from a DUT (Device under test) to analyze fail bits in the DUT. The FM temporarily stores therein the fail bit map and then transfers the fail bit map to an external storage having a sufficiently large capacity for a fail bit analysis. However, a long time is required to transfer the fail bit map from the FM to the external storage. Also at the time of a defect analysis, a long time is required to transfer data between the FM and the external storage. Therefore, a fast analysis of fail bits performed inside the memory test apparatus is demanded.
To meet this demand, it is considered that a fail bit analysis is performed using the FM in the memory test apparatus. However, the FM is often constituted of a memory such as an SDRAM (Synchronous Dynamic Random Access Memory) having a high-speed interface and the capacity is smaller than that of the external storage. In this case, the FM cannot store therein the fail bit map of the whole DUT at one time if the capacity of the DUT becomes large.
It is also conceivable to increase the number of SDRAMs in the FM. In this case, however, the mounting area of the FM is enlarged.